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Verification Techniques for System-Level Design (Margan Kaufmann Series in Systems on Silicon)
This book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design
errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL).This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. This is the first book that covers all aspects of formal and semi-formal, high-level (higher than RTL) design verification targeting SoC designs. It offers formal verification of high-level designs (RTL or higher) and discusses verification techniques with associated system-level design methodology.
Brief Description:
Covers different aspects of high-level formal and semi-formal verification techniques for system level designs. This book offers formal verification of high-level designs (RTL or higher) and discusses verification techniques with associated system-level design methodology.
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