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VLSI Test Principles & Architectures: Design for Testability
This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.
* Most up-to-date coverage of design for testability.
* Coverage of industry practices commonly found in commercial
DFT tools but not discussed in other books.
* Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
* Lecture slides for Chapters 1-5 and exercise solutions for Chapters 1, 2, 3 & 5 are available now.
* Lecture slides and exercise solutions for the remaining chapters will be available by September 15, 2006.
Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation
Chapter 4 - Test Generation
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age
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